One of the primary goals of memory manufacturers is increasing the storage density of memory devices. Improvements in integrated circuit fabrication techniques can achieve this goal by reducing the sizes of integrated circuit structures. Accordingly, as fabrication techniques improve, manufacturers can often increase memory densities simply by making the same memory structures smaller. Another technique for improving storage density is improving the functionality of memory structures to provide more storage per area. This can be achieved, for example, by creating memory cells and peripheral memory circuits that are capable of storing more information per memory cell.
U.S. Pat. No. 6,011,725, entitled “Two Bit Non-Volatile Electrically Erasable and Programmable Semiconductor Memory Cell Utilizing Asymmetrical Charge Trapping” describes a non-volatile memory that stores two bits per memory cell. FIG. 1 shows a memory cell 100 such as described in U.S. Pat. No. 6,011,725. Memory cell 100 includes diffused N+ source/drain regions 120A and 120B in a silicon substrate 110, a gate insulator 130 overlying substrate 110, and a gate 150 overlying gate insulator 130. Gate insulator 130 has an ONO structure including a silicon nitride region 140 sandwiched between silicon dioxide regions 132 and 134.
Two bits of data are stored in memory cell 100 as charge that is trapped in separated and isolated locations 140A and 140B in nitride region 140. Each location 140A or 140B corresponds to a bit having a value 0 or 1 according to the state of trapped charge at the location 140A or 140B. To program cell 100, gate 150 is raised to a high voltage while a channel current passes between diffused regions 120A and 120B and injects charge into nitride region 140. The location 140A or 140B of the injected charge depends on the characteristics of memory cell 100, the applied voltages, and whether the channel current flows from region 120A to region 120B or from region 120B to region 120A. The direction of the channel current during a programming operation thus selects which of the bits (i.e., location 140A or 140B) is programmed.
Reading a data bit from a particular location 140A or 140B is accomplished by biasing gate 150 at a voltage that is above the threshold voltage of memory cell 100 when locations 140A and 140B are in an unprogrammed state. The diffused region 120A or 120B that is closest to the location 140A or 140B being read is biased as the source/region for the read operation. Any charge trapped in locations 140A and 140B affects a portion of the underlying channel so that negative charge trapped near the source effectively reduces the gate-to-source voltage and correspondingly reduces the channel current during the read operation. In contrast, negative charge near the drain region is ineffective at reducing the channel current since an appropriate drain voltage effectively punches through the portion of the channel near the drain. Sensing whether a channel current flows in memory cell 100 during the read indicates the value of the bit associated with the location 140A or 140B nearest the source/region 120A or 120B.
Memory cell 100 has the advantage of providing non-volatile storage of two bits of information in a single-transistor memory cell, increasing the storage density when compared to a memory device storing one bit of data per storage transistor. However, scaling memory cell 100 down to smaller feature sizes may present difficulties. In particular, operation of memory cell 100 requires the ability to inject charge into separate locations 140A and 140B in nitride region 140. As the size of nitride region 140 decreases, the shorter distance between locations 140A and 140B may be unable to accommodate lateral charge movement after the write operation. Additionally, the amount of charge trapped at locations 140A and 140B of nitride region 140 is relatively small (e.g., typically a few hundred electrons) when compared, for example, to the charge (e.g., typically tens of thousands of electrons) in the floating gate of a conventional Flash memory cell. The smaller trapped charge makes precise control of threshold voltages more difficult because small variations in the trapped charge have large effects. This renders analog or multi-bit storage at each location 140A or 140B in memory cell 100 substantially more difficult than analog or multi-bit storage in a conventional Flash memory cell.